Subject: Raw processor seminar, MIT, 8/17
From: Mitchell Wand (wand@ccs.neu.edu)
Date: Thu Aug 16 2001 - 13:24:41 EDT
A little off-topic and a little short notice, but I thought it might
be interesting... --Mitch
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Subject: FW: Seminar on Aug. 17, 6th floor playroom
Date: Thu, 16 Aug 2001 11:11:09 -0400
> Seminar: Colloqium on Computer Architecture and Compiler Technology
August 17, 2001
4:00 PM
6th Floor Playroom
>
Michael Taylor
>
> The Raw Processor: A Scalable 32-Bit Fabric for Embedded and
> General Purpose Computing
>
> Computer architects rely on a hierarchy of abstraction barriers to
> manage the complicated task of mapping a class of computation down
> on to a convenient physical phenomenon. Recently, three
> technological forces have been crashing through these barriers: wire
> delay, the increasing abundance of resources (gates, wires, and
> pins), and power.
>
> The Raw architecture proposes a parallel, scalable ISA that exposes
> wire delay, gates, wires, pins and power consumption directly to the
> operating system, compiler or programmer. The ISA ensures that wire
> lengths, design complexity and verification complexity are all
> independent of the transistor count. Additionally, the ISA ensures
> that the resources available to the programmer scale linearly with
> the actual physical resources (gates, wires, and pins.)
>
> The Raw architecture specifies a carefully selected set of
> architectural mechanisms that allow the programmer to coordinate
> these exposed resources. This allows Raw to support general purpose
> computations as well as computations that have traditionally been
> consigned to special purpose DSPs, FPGAs or ASICs.
>
> The Raw prototype has been implemented in the .15 micron IBM SA-27E
> ASIC process. The design occupies an 18.2x18.2mm die, has 1080 HSTL
> signal I/Os, consumes 25W, and runs at a target frequency of 225
> MHz.
>
> This talk will present details of the Raw design and show how it
> addresses these technological forces.
>
>
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