Future Memory Technologies

For the systems seminar, this Friday, Nov. 15 (3:30, 149 CN), we will discuss future memory technologies, and the prognosis for the CPU-memory gap. I've divided this into three sections: Background, Near-term technologies, and Future technologies. I will talk on Background, and I will then open up the discussion to issues of near- and future technologies. As preparation, I'd like each of you to just pick a link beyond the background links (pick any one), and skim through it to get the flavor. In the following week, we can pick out some articles to look at in depth.

Background

Memory latency is comprised of 1) address decoding delay, 2) word line delay, 3) bit line sensing delay, and 4) output driving delay.

In more detail (taken from Ace's Guide to Memory Technology: Part 1): Basically, the latency of the whole memory (From FSB to DRAM) system is equal to the sum of:

1. The latency between the FSB and the chipset (+/- 1 clockcycle)
2. The latency between the chipset and the DRAM (+/- 1 clockcycle)
3. The RAS to CAS latency (2-3 clocks, charging the right row)
4. The CAS latency (2-3 clocks, getting the right column)
5. 1 cycle to transfer the data.
6. The latency to get this data back from the DRAM output buffer to the CPU (via the chipset) (+/- 2 clockcycles)

• Ace's Guide to Memory Technology: Part 1
• Ars Technica RAM Guide
• Ars Technica RAM Guide (Part 2)
• ArtsTechnica.com
• X86-secret.com : Tous les secrets des constructeurs (French)

1. limitations on bus width:
   bus skew --- the wider the bus, the more likely that signals on one line will not be timed correctly with signals on another line.
2. limitations of bus latency and energy dissipation:
   the chip must develop enough charge on each pin before sending out the signal --- as chips use lower and lower voltages, this process can take longer.
3. limitations on bus speed:
   when the electricity does not have enough time to travel the length of the wire during one bus cycle, then the standard electrical transmission must be modelled as a transmission line (different voltage levels at different places on the wire during one instant). Transmission lines are likely to be very difficult to engineer on a motherboard.

Good General Papers on understanding today's and Near-Term Technologies

• Reducing DRAM Access Latency
• IDF Fall 2002: Dual Channel DDR, DDR-II, and RDRAM
• Ace's Guide to Memory Technology: Part 2 (DDR RAM and Rambus RAM (RDRAM))
• Ace's Guide to Memory Technology: Part 3 (RDRAM, DDR400 and DDR-II)
• Ars Technica RAM Guide (Part 3, DDR DRAM and Rambus RAM)
• RLDRAM (Reduced Latency DRAM) by Micron and Infineon (and alt)
• FCRAM (Fast Cycle RAM, aka NetRAM, Fujitsu and Toshiba)
• Ars Technica: MRAM (magnetic RAM)
• Ars Technica: embedded DRAM
• ESDRAM: Ramtron/Enhanced Memory Systems, Inc. Enhanced Memory Systems develops and markets patented EDRAMÒ high performance specialty memories that combine fast DRAM and SRAM on one chip. Enhanced Memory Systems is headquartered in Colorado Springs, Colorado and is a wholly owned subsidiary of Ramtron International Corporation (Nasdaq: RMTR).
• WCDRAM: A fully associative integrated Cached-DRAM with wide cache lines (1997), Gershon Kedem, Ram Prasad Koganti
• Vector IRAM: A VLSI Architecture for Media Processing

Future memory technologies

• Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering
• Embedded DRAM page with pointers to various projects
  • Galileo Group (Computer Architecture)
    • * Datascalar: A Memory-Centric Approach to Computing Stefanos Kaxiras, Doug Burger, James R. Goodman Journal of Systems Architecture, Special Issue on Microprocessor Architecture, 45 (1999) pp. 1001-1022.
    • * Limited Bandwidth to Affect Processor Design (or PDF) Doug Burger, James R. Goodman, and Alain Kägi. Invited paper to IEEE Micro, special issue on advanced memory architectures, 17 (6), November/December, 1997.
    • * DataScalar Architectures Doug Burger, Stefanos Kaxiras, and James R. Goodman. Proceedings of the 24th International Symposium on Computer Architecture (ISCA), June, 1997.
    • * Memory Bandwidth Limitations of Future Microprocessors Doug Burger, James R. Goodman, and Alain Kägi. Proceedings of the 23rd International Symposium on Computer Architecture, May, 1996.
  • IRAM
    Intelligent RAM: (We predict that over the next decade processors and memory will be merged onto a single chip. Not only will this narrow or altogether remove the processor-memory performance gap, it will have the following additional benefits: provide an ideal building-block for parallel processing, amortize the costs of fabrication lines, and better utilize the phenomenal number of transistors that can be placed on a single chip. Let's dub it an "IRAM", for Intelligent RAM, since most of transistors on this merged chip will be devoted to memory.)
    • "A Case for Intelligent DRAM: IRAM," IEEE Micro , April 1997.
    • An Overview of Intelligent RAM (IRAM) Tutorial on Merging DRAM and Logic at ASP-DAC '98, February 10, 1998.
  • CRAM (Computational RAM, place many SIMD processors on RAM chip to do limited vector processing on the RAM chip; This avoids the severe memory bandwidth/latency penalty)
    • Computational Ram: A Memory-SIMD Hybrid and its Application to DSP
  • Note other technologies from link to Embedded DRAM page, above